An accuration delay modeling technique for switch-level timing verification

Abstract

A new delay modeling technique for accurate timing verification of digital MOS circuits is presented. The technique is based on the ELogic approach and provides the user with a continuous speed-accuracy trade-off in addition to more accurate timing information than available with existing switch-level timing verifiers. The new technique has been implemented in the Crystal timing analyzer and experimental results comparing this method with those used in Crystal are included. Comparisons indicate that the ELogic-based approach, while slower than present approaches, provides a more robust and more accurate delay analysis at the switch level.