A digital multiprocessor hardware accelerator board for cellular neural networks: CNN‐HAC

Abstract

Abstract Analogue realizations of neural networks are superior in speed. the hardware accelerator boards using catalogue programmable VLSI ICs represent a trade‐off having higher reconfigurability and lower cost. This paper presents such a solution for a cellular neural network (CNN). The architecture of the present design (CNN‐HAC) using four standard DSPs to calculate the transient response of a one‐layer CNN containing (0.25–0.75) × 10 6 analogue neural cells (depending on the type of template) is presented. the architecture and also the design principles are independent of the number of processors. the actual design was made in the form of a PC add‐on board. The global control unit, which connects the board to the host firmware and communicates control signals to/from the local control units of the DSPs, was realized mainly with EPLDs. A special correspondence between the virtual processing elements—calculating the time‐discrete models of the analogue neural cells—and the physical ones is discussed in detail. It is realized in an architecture with a simple, two‐directional interprocessor communication. This architecture can be ‘scaled down’ using faster processors, EPLDs and memories. the present version runs with 2 μs/cell/iteration speed.