Series resistance modeling for optimum design of LDD transistors

Abstract

The characteristics of lightly doped drain transistors are presented and compared with conventional devices. A technique for modeling these devices is then described. We show that LDD transistors have lower substrate currents resulting in improved reliability. The amount of the reduction depends on the the source/drain resistance, However we show that this resistance can have a large effect on circuit performance and that the trade off between circuit response and substrate currents must be carefully evaluated. This understanding allows us to fabricate circuits with a minimum number of process iterations.