Phase-Change Memory Optimization for Green Cloud with Genetic Algorithm

TLDR

Green cloud computing relies on memory, and phase‑change memory (PCM) is a promising DRAM alternative, especially multi‑level cell (MLC) PCM that stores multiple bits per cell but suffers performance degradation compared to single‑level cell PCM due to longer access times. The study proposes a genetic‑based optimization algorithm for chip multiprocessors with PCM memory in green clouds. The algorithm schedules and assigns tasks to CMP cores while configuring PCM MLC cells to balance memory performance and efficiency. Experimental results show the algorithm reduces maximum memory usage by 76.8 % versus uniform SLC, increases memory‑usage efficiency by 127 % versus uniform 4‑bit MLC, and improves total execution time by 24.5 % versus uniform 4‑bit MLC.

Abstract

Green cloud is an emerging new technology in the computing world in which memory is a critical component. Phase-change memory (PCM) is one of the most promising alternative techniques to the dynamic random access memory (DRAM) that faces the scalability wall. Recent research has been focusing on the multi-level cell (MLC) of PCM. By precisely arranging multiple levels of resistance inside a PCM cell, more than one bit of data can be stored in one single PCM cell. However, the MLC PCM suffers from the degradation of performance compared to the single-level cell(SLC) PCM, due to the longer memory access time. In this paper, we present a genetic-based optimization algorithm for chip multiprocessor (CMP) equipped with PCM memory in green clouds. The proposed genetic-based algorithm not only schedules and assigns tasks to cores in the CMP system, but also provides a PCM MLC configuration that balances the PCM memory performance as well as the efficiency. The experimental results show that our genetic-based algorithm can significantly reduce the maximum memory usage by 76.8 percent comparing with the uniform SLC configuration, and improve the efficiency of memory usage by 127 percent comparing with the uniform 4 bits/cell MLC configuration. Moreover, the performance of the system is also improved by 24.5 percent comparing with the uniform 4 bits/cell MLC configuration in terms of total execution time.