A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

Robert Bogdan Staszewski, Dirk Leipold, Oren Eliezer, Mitch Entezari, K. Muhammad, Imran Bashir, Chih-Ming Hung, J. Wallberg, Robert Bogdan Staszewski, P. Cruise,

2008 · 62 citations · 5 references

Concepts

Abstract

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

References

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