IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014 · 28 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryComputer SecurityLow-power DesignLow-power Digital Circuit DesignPower OptimizationSide-channel AnalysisSide-channel AttacksCircuit TopologyDifferential Power AnalysisPower Analysis CountermeasuresSecurity GatesSide-channel Resistant Design
Side channel attacks have become one of the most significant problems in modern digital systems. In particular, differential power analysis (DPA) has emerged as a powerful technique because it does not require any assumptions regarding the hardware implementation of a crypto-chip. In this paper, a new randomized multitopology logic (RMTL) is proposed to enhance immunity to DPA. RMTL refers to a family of dedicated security-oriented gates whose power profile cannot be predicted by external observers. Specifically, each gate of this logic can be configured in real time to operate in a different circuit topology, where each topology induces a different power profile. Immunity to DPA attacks is obtained by randomly changing each gate's topology on run time. The suggested approach can coexist with common existing countermeasures. Theoretical analysis and simulation results, conducted in a standard 40-nm technology, clearly show higher immunity to DPA attacks when using the proposed approach compared with standard CMOS implementation.
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