Radiation Hardened CMOS/SOS

Abstract

This paper reports the results of experiments designed to optimize the total dose ionizing radiation hardness of CMOS/SOS devices. Type 4007 inverter circuits were fabricated with variations in the process, including wet versus dry gate oxidation. Tolerable values (e. g. < l#x003BC;A per mil of channel width) of post-radiation n-channel back leakage were obtained only with wet oxides. Threshold shifts of ≤1V for the n-channel devices and ≤2V for the p-channel devices were obtained after 106 rads (Si) on the best devices fabricated.