2011 · 10 citations · 2 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureReconfigurable ComputingSystem-on-chip DesignField-programmable Gate Array ArchitectureFpga ArchitectureMemory Subsystem DesignNetwork-on-chip DesignReconfigurable Embedded SystemsReconfigurable System ArchitectureAdaptive Image ProcessingAddress Space ManagementAddress Space MappingNetwork-on-chipNetwork-on-chip ArchitecturesReconfigurable Computing ArchitecturesReconfigurable Image Processing SystemsReconfigurable System-on-chip Architectures
This paper presents a novel approach for a memory, which supports the flexibility of an FPGA-based dynamic reconfigurable System-on-Chip consisting of heterogeneous data processing nodes. The memory is accessible via the Network-on-Chip (NoC) and provides a dynamic mapping of address space for the different clients within the network. Different data transfer modes support especially the image processing domain where burst transfers to the processing nodes are required. The presented method and realization overcomes the well known difficulties in FPGA-based multiprocessor systems, which are the restricted on-chip memory and the fact, that normally only one physical channel to an off-chip memory is available.
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Programming the FlexRAM parallel intelligent memory system
Basilio B. Fraguela, Jose Renau, Paul Feautrier et al. · 2003 · 27 citations
Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip
Diana Göhringer, Oliver Oey, Michael Hübner et al. · 2011 · 14 citations