A fast and low power multiplier architecture

Abstract

In this paper a new multiplier architecture is proposed for low power and high speed applications. It is based on generating all partial products in one step, then summing these partial products using binary tree network. This reveals a speedup of more than 50% than the array multiplier for (32/spl times/32) bit multiplication. Computer simulation with HSPICE shows that the new proposed architecture has better speed and power performance.