A [100] silicon stress test chip with optimized piezoresistive sensor rosettes

Abstract

A new piezoresistive stress sensing test chip for use on (100) silicon wafers is discussed. The die design contains four-element dual-polarity rosettes optimized for use in measurement of the in-plane normal stress difference (/spl sigma//sub 11//sup '/-/spl sigma//sub 22//sup '/) and the in-plane shear stress /spl sigma//sub 12//sup '/. The rosettes offer high sensitivity to stress since their outputs are proportional to the largest piezoresistive coefficients, /spl pi//sub 44/ in p-type silicon and /spl pi//sub D/ in the n-type silicon. The rosette outputs are both temperature compensated and insensitive to rotational alignment errors and are independent of the out-of-plane normal stress /spl sigma//sub 33/'. Thus, they may be used to measure the in-plane stress components in plastic encapsulated packages where /spl sigma//sub 33/' is not zero. Three-element off-axis p-type and n-type rosettes are also included on each chip for use in uniaxial calibration of the required piezoresistive coefficients. The properties of these rosettes are reviewed, and it is shown that the off-axis rosette yields temperature compensated calibration of the values of /spl pi//sub 44/ and /spl pi//sub D/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>