Improved wafer-level spatial analysis for I/sub DDQ/ limit setting

Abstract

This paper proposes a new methodology for estimating the upper bound on the I/sub DDQ/ of defect free chips by using wafer level spatial information. This can be used for I/sub DDQ/ pass/fail limit setting. This methodology is validated using SEMATECH data. Such a methodology accounts for the change in I/sub DDQ/ due to process variations across wafers and reduces false rejects resulting in yield loss. Typical scenarios in using this approach are discussed. The results are compared with traditional methods.