A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level

Abstract

A 30 MHz, 30 mW, 0.3 mm/sup 2/ DDS clock generator circuit with time domain interpolation and -50 dBc spurious signal level has been designed. The sine look-up-table and D/A converter of the conventional DDS have been replaced by a three-step digitally programmable delay generator with 130 ps resolution. This increases the effective sampling frequency to 7.68 GHz, and that's why no reconstruction filters are needed to create output square wave clock signal.