2002 · 36 citations · 9 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureClock Distribution NetworksClock ManagementDigital Logic DesignTiming AnalysisClock Skew CorrectionClock Skew MinimizationHigh-speed Cmos DesignHigh-speed Logic Design
This paper presents skew-tolerant high-speed domino logic. Skew-tolerant high-speed domino logic resolves the floating dynamic node problem of high-speed domino logic and alleviates the strict clock timing requirement. Simulation results show that skew-tolerant high-speed domino logic is more robust to noise and timing variation than high-speed domino logic, while achieving better performance.
9
Noise in deep submicron digital design
Kenneth L. Shepard, V. Narayanan · 1996 · 283 citations
Engineering, Computer Engineering, Electrical Engineering +17
Noise in deep submicron digital design
Kenneth L. Shepard, V. Narayanan · 2002 · 230 citations
Engineering, Computer Engineering, Electrical Engineering +17