An analog VLSI decoding technique for digital codes

Abstract

Iterative decoding of high-performance error-correcting codes, such as turbo and related codes, is computationally demanding. This paper presents the application of a new type of analog computing network that enables the construction of all-analog decoders for such codes which outperform digital decoders in terms of speed and/or power consumption. The analog networks are based on the observation that certain computations with probabilities are naturally carried out by elementary transistor circuits. As an illustrative example, a complete decoder circuit for a simple tail-biting trellis code is given. Practical implementation issues such as device and thermal mismatch are also discussed.