Formulation of INL and DNL yield estimation in current-steering D/A converters

Abstract

Current source mismatch is a major source of nonlinearity in current-steering digital-to-analog converters (DAC). In order to achieve a given linearity specification at a given yield level, it is essential that the designer determine the:: minimum required matching accuracy of the unit current sources. Monte-Carlo simulations are very time-consuming and provide the designer with little insight to choose proper DAC architectures and make tradeoff between design specifications. The limited mathematical formulations that have appeared in the literature are based on nonstandard linearity definitions or oversimplifying statistical assumptions. In this paper, simple formulas are obtained that accurately describe the relationship between nonlinearity, bits of resolution, minimum required matching accuracy, and yield, which make it possible to optimize the DAC structure and achieve high performance with less cost and power consumption.