2002 · 28 citations · 9 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMicroelectronicsSystem-on-chip DesignCluster ArchitectureEmbedded Memory BlocksMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignProgrammable ArchitectureStatic Random-access Memory Design
This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.
9
A distributed BIST control scheme for complex VLSI devices
Y. Zorian · 2002 · 543 citations
Engineering, Computer Engineering, Electrical Engineering +12
March tests for word-oriented memories
A.J. van de Goor, I.B.S. Tlili · 1998 · 70 citations
Built-in self-testing of random-access memories
M. Franklin, Kewal K. Saluja · Computer · 1990 · 51 citations · Full text