An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits

Abstract

Monolithic 3D (M3D) integration technology offers fine grain gate level stacking capability compared to 3D Through Silicon Vias (3D-TSV) which is well adapted for coarse-grain applications. As a result, design partitioning, i.e. Which cell on which tier, highly affects the 3D design performance. Previous partitioning methodologies focus on minimizing number of 3D interconnects for equal area ratio between the stacked partitions. This paper demonstrates that un-balancing the tier to tier area ratio of the M3D design brings better performance than classical balanced 3D design approach. Our study highlights that neither balanced area ratio nor the number of 3D interconnections remains mandatory criteria for M3D. We show that our technique can achieve up to 24% performance improvement compared to 2D and 15% better performance than the state-of-the-art technique without extra power penalty.