IEEE Transactions on Circuits & Systems II Express Briefs · 2015 · 72 citations · 16 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsMachine LearningDeep LearningHardware AccelerationNeural NetworksBit-plane CodingHardware ResourcesNeural Network ModelingSystem LatencyTraining
A hardware-efficient sigmoid function calculator with adjustable precision for neural network and deep-learning applications is proposed in this brief. By adopting the bit-plane format of the input and output values, the computational latency of the processing time can be dynamically reduced according to the user configuration. To reduce the hardware cost, the coefficients used to calculate the sigmoid value can be shared for multiple calculators without any structural hazard. In addition, the restricted constraint is applied in the coefficients' training stage to further simplify the computation in the calculation stage with a negligible quality loss. A test module is designed for the proposal and operated at 300 MHz to achieve 75 million sigmoid calculations per second. Implemented in 90-nm CMOS technology, the core of the calculator costs 1663 gates, and a 1-kb globally shared memory is used to store the coefficients.
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