2002 · 26 citations · 5 references
EngineeringElectrical EngineeringMicroelectronicsMicrowave EngineeringWireless CommunicationsCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyHigh-frequency Semiconductor DevicesIntegrated Circuit DesignMicrowave Integrated CircuitsRadio-frequency Integrated CircuitsCmos Radio-frequency CircuitsInductorsNoise FigureQuality Factor OptimizationRadio-frequency Integrated Circuit DesignRf Cmos DesignSubstrate Noise CouplingTransconductance
This paper presents a high performance RF CMOS technology with a complete portfolio of RF and base band components for single-chip systems. Using optimized CMOS topology and deep n-well isolation, we obtain a F/sub t/ of 60 GHz and F/sub max/ of 55 GHz at 10 mA, a F/sub t/ of 70 GHz and F/sub max/ of 58 GHz at maximum-transconductance bias, and minimum noise figure of 1.5 dB without ground-shielded signal pad. High quality-factor inductors are obtained using Cu interconnect giving a quality factor of 18 at 1.7 nH. MIM capacitors, as well as accumulation and junction varactors are also optimized for enhancing quality factor. For the purpose of eliminating inter-block coupling noise penetrating through substrate, a deep n-well isolation and p-ring have been adopted to suppress the substrate noise by 25 dB and 10 dB respectively. This technology provides a complete solution for single-chip wireless systems.
5
A highly efficient 1.9-GHz Si high-power MOS amplifier
Isao Yoshida, M. Katsueda, Y. Maruyama et al. · IEEE Transactions on Electron Devices · 1998 · 38 citations
A high Q on-chip Cu inductor post process for Si integrated circuits
John Rogers, Liang Z. Tan, T. Smy et al. · 2003 · 15 citations
Engineering, Electrical Engineering, Materials Engineering +17