Performance of 70 nm strained-silicon CMOS devices

Abstract

An 86% electron mobility improvement and over 20% I/sub dn-sat/ enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage through a 16 /spl Aring/ nitrided oxide, which remained the dominant leakage source despite dislocation-induced junction leakage observed on strained-Si wafers. Self-heating of strained-Si CMOS due to the low thermal conductivity SiGe virtual substrate reduces I/sub dn-sat/ by 7% during DC operation.