A test point insertion method to reduce the number of test patterns

Abstract

The recent advances in semiconductor integration technology have resulted in an increasing number of the test lengths of full scan designed LSI. This paper presents a test point insertion method for reducing test patterns of full scan designed LSI. In our method, test points are inserted based on improved fault detection probability and value assignment probability such that test patterns are efficiently compacted. Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%. Those results also prove that our method is very effective for reducing the number of test patterns.