A 64x64 aer logarithmic temporal derivative silicon retina

TLDR

Real‑time artificial vision is limited by frame rate, yet many frames contain redundant information within and across time. The study reports the development of an AER silicon retina chip, TMPDIFF, that generates events for changes in log intensity. TMPDIFF uses a 64×64 array of self‑clocked switched‑capacitor pixels, each with ON/OFF outputs, fabricated in a 0.35 µm 4M 2P process, and outputs address events asynchronously on a shared 13‑bit digital bus, providing a dynamic range of ≥5 decades and sensitivity below 10 lux. The chip delivers high temporal resolution with low spatial resolution, mimicking the magnocellular pathway, and consumes only 7 mW.

Abstract

Real time artificial vision is traditionally limited to the frame rate. In many scenarios most frames contain information redundant both within and across frames. Here we report on the development of an Address-Event Representation (AER) [1] silicon retina chip `TMPDIFF’ that generates events corresponding to changes in log intensity. The resulting address-events are output asynchronously on a shared digital bus. This chip responds with high temporal and low spatial resolution, analogous to the biological magnocellular pathway. It has 64x64 pixels, each with 2 outputs (ON and OFF), which are communicated off-chip on a 13-bit digital bus. It is fabricated in a 0.35u 4M 2P process and occupies an area of (3.3 mm). Each (40u) pixel has 28 transistors and 3 capacitors and uses a self-clocked switched-capacitor design to limit response FPN. Dynamic operating range is at least 5 decades and minimum scene illumination with f/1.4 lens is less than 10 lux. Chip power consumption is 7mW.