Highly parallel increment/decrement using CMOS technology

Abstract

A design technique for the construction of an incrementer/decrementer circuit is presented. The technique is shown to be highly efficient both in terms of space and time. There are two basic operations involved in this technique: (1) finding the least significant zero bit (LSZB), and (2) inverting all bits below LSZB including LSZB. For the first part, a network of priority resolution (PR) modules is implemented which is new in structure, and the modules operate concurrently. For the second part, selector modules which produce inverted or non-inverted bits, depending on the selector code value, are used. A 64-bit incrementer circuit is being designed using MOSIS CMOS3 technology. The simulation result of the proposed design is encouraging and indicates the high efficiency of the device.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>