IEEE Journal of Solid-State Circuits · 1982 · 34 citations · 4 references
Hardware SecuritySystem On ChipElectrical EngineeringEngineeringVlsi DesignTimes/32 Bit MultiplicationVlsi ArchitectureComputer ArchitectureComputer EngineeringAdvanced Nmos TechnologyOn-chip Control RomDigital Circuit DesignMicroelectronicsProcessor ArchitectureInstruction Decoding
The circuit and design of an experimental 32-bit execution unit are described. It is fabricated in a scaled NMOS single-layer poly-technology with 2-/spl mu/m minimum gate length and low-ohmic polycide for gates and interconnections. The chip (25000 transistors, 16 mm/SUP 2/, 61 pins) is designed with a high degree of regularity and modularity. The circuit performs logic and arithmetic operations and has an on-chip control ROM for instruction decoding. It operates with a single 5-V supply voltage. Measurements resulted in a typical power dissipation of 750 mW and a maximum operation frequency of 6.5 MHz. At this frequency a 32/spl times/32 bit multiplication is performed in less than 5.5 /spl mu/s.
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