IEEE Transactions on Applied Superconductivity · 1999 · 45 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock Distribution NetworksClock ManagementCmos Circuit DesignHigh-frequency Semiconductor DevicesLow-power Digital Circuit DesignTiming AnalysisBlock RamBlock Ram ArchitectureClock DesignClock DistributionHigh-frequency OperationHigh-speed OperationLow-power Memory ArchitectureLow-power Memory Circuits
A Josephson 256-word/spl times/16-bit RAM that includes a power circuit has been developed to enable high-frequency clock operation. This RAM consists of a 4/spl times/4 matrix array of 256 RAM blocks, impedance-matched lines, and signal amplifiers. A power-supply circuit, composed of a transformer and a Josephson regulator, is included in each 256 RAM block. Fail bit maps for the 256 RAM block were measured, and perfect operation with a 100% bit yield was obtained. The 256 RAM block functioned up to a clock frequency of 1.07 GHz. We succeeded in feeding a large high-frequency current of more than 2 A into the entire 256-word/spl times/16-bit RAM. The 256-word/spl times/16-bit RAM therefore functioned up to a clock frequency of 620 MHz.
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Hideo Suzuki, Norio Fujimaki, Hirotaka Tamura et al. · IEEE Transactions on Magnetics · 1989 · 51 citations
Engineering, Computer Engineering, Electrical Engineering +15