Publication | Closed Access
GMICRO/500 microprocessor: pipeline structure of superscalar architecture
10
Citations
6
References
2003
Year
Unknown Venue
EngineeringCompiler TechnologyComputer ArchitectureSystem-level DesignProcessor ArchitectureHardware SystemsPipe Bypass MechanismHigh-performance ArchitectureParallel ComputingCompilersManycore ProcessorInstruction-level ParallelismComputer EngineeringComputer ScienceInstruction Execution MechanismGmicro/500 MicroprocessorOperating SystemsOverall Gmicro/500 PerformanceMany-core Architecture
The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed, illustrating the effect of a pipe bypass mechanism and dedicated resident branch instruction caches. The benefit of microprogram-controlled instruction execution for high-speed execution of high-level language instructions is shown. Overall GMICRO/500 performance is evaluated in Dhrystones.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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