Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems

Abstract

This paper presents an original approach to the implementation of a fault-tolerant FPGA-based system. In particular, we consider the conventional Triple Modular Redundancy fault-tolerance technique and address practical problems related to its actual implementation into FPGA devices. All possible functional faults affecting the used FPGAs are either tolerated or on-line detected. Differently from conventional VLSI fault-tolerant systems, here the FPGA possible reconfigurability is exploited to ensure the continuity of operation for a high number of possible internal faults, without requiring further replications (besides the three basic copies) of the considered device.