An improved bang-bang phase detector for clock and data recovery applications

Abstract

A low power fully integrated PLL-based 5 Gb/s NRZ clock and data recovery circuit was successfully implemented in a 0.18 /spl mu/m CMOS process. A novel bang-bang phase detector, used in the implementation, resulted in improved jitter performance compared to conventional bang-bang detectors. Differential topologies were used for the charge-pump and VCO circuits to reduce the design sensitivity to power supply noise. The maximum measured clock jitter from a 2/sup 23/-1 pseudorandom bit stream (PRBS) input data was less than 4.8 ps rms. The total power dissipation was less than 80 mW from a 1.8 V supply.