A configurable CMOS memory platform for 3D-integrated memristors

Abstract

Memristors are emerging as powerful nanoscale devices for diverse applications, such as high-density memories and neuromorphic applications. However, this nascent technology requires considerable advancement before this vision is realized. We present a highly configurable CMOS interface chip which enables the characterization of on-chip memristors, especially for memory applications. The chip was fabricated in On-Semi 3M2P 0.5 μm occupying 2×2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The chip design allows for post-CMOS fabrication of memristors. The interface between the memristor and the CMOS circuitry was provided via a top metal contact. The chip was designed to support an area-distributed interface decoupling CMOS pitch and memristor pitch, enabling high-density memristor integration. Measurement results on post-CMOS fabricated Ag/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Pt memristive devices are reported. Though we have shown the results from one memristive material stack, thorough chip characterization demonstrates the versatility of the chip enabling its use with a wide variety of materials stacks.