2006 · 14 citations · 4 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsHardware Description LanguagesNetwork-on-chip DesignNeural CommunicationNeural InterfacesReal-time Systems ArchitectureSpiking Neural NetworksTiming ModelingNeural Interface DesignNeuromorphic DevicesNeuromorphic HardwareOn-chip CommunicationReal-time Hardware ArchitectureSpiking Network ArchitecturesSpiking Neural Network ModelsSpiking Neuron Models
Address event representation (AER) is a neuromorphic interchip communication protocol that allows for real-time connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (nano-seconds), synaptic neural connections can be time multiplexed (mili-seconds). When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows: (a) to read AER interchip traffic; and (b) inject a sequence of events to the AER structure. This paper presents a PCI to AER interface, that dispatches a sequence of events with timing information. It is able to recovery the possible delays introduced by AER bus. It has been implemented in real time hardware using VHDL and tested in a PCI-AER board, developed by authors, that currently capable to send and receive events at a peak rate of 16 Mev/sec, and a typical rate of 10 Mev/sec
4
On algorithmic rate-coded AER generation
Alejandro Linares-Barranco, G. Jiménez, B. Linares-Barranco et al. · IEEE Transactions on Neural Networks · 2006 · 70 citations · Full text
Retinomorphic Vision Systems 11: Communication Channel Design
Kwabena Boahen · 2005 · 32 citations · Full text