DRAMA: An Architecture for Accelerated Processing Near Memory

TLDR

Data movement between storage and processing consumes a large share of energy, so reducing transfers across the memory hierarchy can markedly improve system energy efficiency. The authors propose DRAMA, an architecture that 3‑D stacks coarse‑grain reconfigurable accelerators on off‑chip DRAM to cut data movement. DRAMA connects the CGRA layer to the DRAM’s internal I/O bus via through‑silicon vias, requiring no changes to the DRAM device itself. DRAMA cuts memory‑hierarchy data‑transfer energy by 66–95 % and yields up to 18× speedups over a commodity processor.

Abstract

Improving energy efficiency is crucial for both mobile and high-performance computing systems while a large fraction of total energy is consumed to transfer data between storage and processing units. Thus, reducing data transfers across the memory hierarchy of a processor (i.e., off-chip memory, on-chip caches, and register file) can greatly improve the energy efficiency. To this end, we propose an architecture, DRAMA, that 3D-stacks coarse-grain reconfigurable accelerators (CGRAs) atop off-chip DRAM devices. DRAMA does not require changes to the DRAM device architecture, apart from through-silicon vias (TSVs) that connect the DRAM device's internal I/O bus to the CGRA layer. We demonstrate that DRAMA can reduce the energy consumption to transfer data across the memory hierarchy by 66-95 percent while achieving speedups of up to 18× over a commodity processor.