2002 · 41 citations · 6 references
EngineeringComputer EngineeringComputer ScienceDesign OptimizationLow-power DesignOptimizationDigital Signal ProcessingLow-power Digital Circuit DesignPower DissipationPower ManagementPower OptimizationPower-aware DesignData Bus ArchitectureEnergy-efficient Signal ProcessingFiltersFinite Impulse Response Filter ImplementationFinite Impulse Response FiltersHamming DistanceMultiplier DesignPower-efficient Design
In this paper we present an algorithm for optimizing coefficients of a Finite Impulse Response (FTR) filter, so as to reduce power dissipation of its implementation on a programmable Digital Signal Processor. We first identify the sources of power dissipation and show that the power dissipation depends on the total Hamming distance between successive coefficient values. We then present an algorithm that optimizes coefficients so as to minimize this measure. Experimental results on six FIR filter examples show that the coefficient optimization algorithm results in upto 36% reduction in the total Hamming distance. This directly translates into reduction in the power dissipation in the coefficient memory data bus and the multiplier.
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Programmable DSP architectures. II
Edward A. Lee · IEEE ASSP Magazine · 1989 · 166 citations
Multiplier policies for digital signal processing
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Programmable DSP architectures. I
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