M*N Booth encoded multiplier generator using optimized Wallace trees

Abstract

The architecture and the design method for an M-*-N Booth-encoded parallel-multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is presented and explained. The final stage of adding two (N+M-1)-bit numbers is done by an optimal carry-select adder stage. An algorithm for optimal partitioning of the (N+M-1)-bit adder is also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>