Ultralow-power CMOS/SOI LSI design for future mobile systems

Abstract

Ultralow-power CMOS/SOI circuit technology that uses fully-depleted SOI and multi-threshold (MT) CMOS circuits makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to 1 /spl sim/ 10 mW without any speed loss. We overview the ultralow-power CMOS/SOI circuit technology and some ultralow-voltage LSIs based on MTCMOS/SOI circuits.