PEAS-III: an ASIP design environment

Abstract

In this paper, an architectural level processor design environment PEAS-III is proposed. Pipelined processors designed by this system can include multi-cycle operation, delayed branch and external interrupt. The data path and control logic of the processor are generated from the clock based micro-operation description of instructions. The ease of large design space exploration through experiments using several subsets of MIPS R3000 instruction set.