NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications

Abstract

State-of-the-art process-strained Si (PSS) technology featuring single-NiSi Schottky source/drain (S/D) and ultra-thin gate oxide of 1.2 nm is demonstrated for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</sub> down to 39 nm. +10% performance boost of Schottky-barrier (SB)-PSS NMOS, as compared to its non-Schottky counterpart, is demonstrated due to series resistance reduction of the silicide S/D and enhanced strain effects. Highest SB-PSS PMOS drive current of 821 muA/mum (at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = -1.2V and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> = 100 nA/mum) is recorded when integrated with recessed Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x </sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> S/D stressor