Mappable peripheral memory for high speed applications

Abstract

A 30-ns mappable peripheral memory subsystem called MAP, is described. The MAP significantly enhances system performance by integrating, on the same chip, a 128-kb EPROM for program storage, a SRAM for data storage, and a programmable mapping decoder (PMD) for address decoding and mapping. The PMD is integrated into the memory-decode logic without adding up the access time. The decoder facilitates address mapping within a 2-Mb address space. The MAP is ideally suited as an expansion peripheral memory for high-speed digital signal processors, microprocessors, and microcontrollers. The 290-mil-sq. chip is implemented in a 1.2- mu m CMOS EPROM process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>