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Experimental studies of metastability behaviors of sub-micron CMOS ASIC flip flops
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2002
Year
Unknown Venue
EngineeringVlsi DesignIntegrated CircuitsMetastability PerformancesMetastability Test CircuitNanoelectronicsElectrical EngineeringPhysicsBias Temperature InstabilityComputer EngineeringMetastability BehaviorsMicroelectronicsLow-power ElectronicsMicrofabricationApplied PhysicsBasic Metastability TheorySemiconductor MemoryExperimental StudiesBeyond Cmos
The author describes the experiment for characterizing metastability performances of sub-micron gate array and cell-based CMOS ASIC flip flops. Basic metastability theory, metastability test circuit, software (flow charts) and hardware set up are discussed. Analyzed experimental results are compared with other technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>