A 200 Mb/s analog DFE read channel

Abstract

A 200 Mb/s read-channel IC realizes an enhanced decision-feedback equalizer (DFE) with a combination of continuous and discrete time analog and digital signal processing. The design uses a 20 GHz peak-f/sub T/, BiCMOS process operating at 5 V, with a power consumption of approximately 700 mW. All associated functions are included: bit detection, RLL encoder/decoder, servo demodulation, and write precompensation. Data rate range is 64200 Mb/s at a normalized recording density of 1.8-2.4.