Linewidth control effects on MOSFET ESD robustness

Abstract

This paper advances state-of-the-art design layout considerations for deep sub-micron (0.25-/spl mu/m) advanced single and stacked MOSFETs by addressing linewidth control effects on MOSFET ESD robustness. Advanced failure analysis tools are used to demonstrate linewidth bias. ESD robustness as a function of gate-to-gate spacings is addressed for the first time.