A CMOS 40 MHz 8 b 105 mW two-step ADC

Abstract

To meet the demand for digital signal processing of wideband video signals, a 40-MHz, 8-b ADC (analog/digital converter) with 105-mW power consumption on a 4.88-mm/sup 2/ chip has been developed using a 1.4- mu m standard-cell CMOS process. To obtain 8-b fast conversion, the ADC uses a sample-and-hold comparator with an averaging feature for differential linearity for high-speed sampling and high-frequency inputs and an expanded fine comparison to increase conversion speed. The block diagram of the converter is shown together with two techniques employed to increase conversion speed. The DC linearity of the converter at a 40-MHz conversion rate is shown. The limit of differential linearity is less than +or-0.5 least significant bit for 8 b. The measured power consumption as a function of sampling frequency and supply voltage is also shown. For 40-MHz sampled at a supply voltage of 5 V, the power consumed is 105 mW. For 14.3-MHz sampling at 3.5 V, the consumption drop to 27 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>