Publication | Closed Access
A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor
11
Citations
2
References
2005
Year
Unknown Venue
EngineeringVlsi DesignRadio FrequencyComputer ArchitectureProcessor ArchitectureElectromagnetic CompatibilityHardware SecurityIntegrated Rf Front-endFirst-generation Cell ProcessorRf SemiconductorHigh-performance ArchitectureMixed-signal Integrated CircuitParallel ComputingElectrical EngineeringFine-grained Clock-gating SupportDouble-precision MultiplierBaw FilterComputer EngineeringMicroelectronicsHardware AccelerationVlsi ArchitectureBaw Filter AreaRf Subsystem
The feasibility of a fully integrated RF front-end using an above-IC BAW integration technique is demonstrated for WCDMA applications. The circuit has a voltage gain of 31.3dB, a noise figure of 5.3dB, an in-band IIP3 of -8dBm and IIP2 of 38dBm, with a total power consumption of 36mW. The BAW filter area is 0.45mm/sup 2/ and the total circuit area including the BAW filter is 2.44mm/sup 2/.
| Year | Citations | |
|---|---|---|
Page 1
Page 1