Design of a 12 GHz Low-Power Extended True Single Phase Clock (E-TSPC) Prescaler in 0.13µm CMOS technology

Abstract

The design of a 12 GHz Low-Power Extended True Single Phase Clock (E-TSPC) Prescaler is presented in this paper. First the function and advantages of the TSPC technique are explained. Examples of basic TSPC structures are given to clarify the functionality. Afterwards the design and implementation of the E-TSPC based Prescaler is shown. This static through-eight divider consists of three divide-by-two E-TSPC stages. The functional principle of the divide-by-two stage is explained. The structure of the E-TSPC divide-by-eight prescaler was manufactured in a 0.13 µm CMOS process from IBM. The measurement results are compared with the expected results from the layout simulations. The design reached a maximum input frequency of 12 GHz with a power consumption of only 0.75 mW. The results are compared to other state of the art E-TSPC dividers showing that the proposed design can reach high speed with low power and low area consumption.