Simulation of junctionless Si nanowire transistors with 3 nm gate length

Abstract

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ∼1 nm wire diameter and ∼3 nm gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.