Concepedia

A novel stack capacitor cell for high density FeRAM compatible with CMOS logic

T. Hayashi, Yasushi Igarashi, D. Inomata, T. Ichimori, T. Mitsuhashi, Kinya Ashikaga, T. Ito, Masaki Yoshimaru, M. Nagata, S. Mitarai,

2003 · 15 citations · 1 references

DOI

Concepts

EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignIntegrated Circuit DesignMos CapacitorsPhysical DesignCmos Digital Circuit DesignCmos Logic CircuitsCmos Logic DesignCmos ScalingDiffusion Barrier DesignMemory Circuit DesignOxidationOxidation Treatment

Abstract

We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.

References

1

Advanced 0.5 μm FRAM device technology with full compatibility of half-micron CMOS logic device

Tatsuya Yamazaki, Ken‐ichi Inoue, Hiroyuki Miyazawa et al. · 2002 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +9