Verification of loop transformations for real time signal processing applications

Abstract

A formal method to verify the loop ordering of a transformed description against its original specification is presented. The method is related to models used in regular array synthesis but is extended with non manifest index expressions. The method is especially suited for applications in the area of speech, image and video processing, front-end telecom and numerical computing systems which exhibit many loops and multidimensional signals. The reordering of the loop organization in these descriptions and the verification of the behavioral equivalence of the reordered description is a complex task which can be done formally and automatically with the presented method. The efficiency of the method is demonstrated on several realistic test vehicles.