20 nm tri-gate SONOS memory cells with multi-level operation

Abstract

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.