A 13ns/500mW 64Kb ECL RAM

Abstract

This paper will cover the design of a 16K×4 SRAM which uses buried twin-well 2μm CMOS transistors and 4GHz cutoff frequency bipolar transistors. The circuit combines a high-resistance polysilicon - load NMOS memory cell with mixed MOS/bipolar periphery circuits to achieve ECL compatibility, 13ns access times and an operating power of 500mW at 40MHz.