Conditional-capture flip-flop technique for statistical power reduction

Abstract

Conventional flip-flops such as hybrid latch-flip-flop (HLFF), semi-dynamic flip-flop (SDFF), and sense amplifier-based flip-flop (SAFF), which are the fastest, are inefficient as far as power consumption is concerned. This is because the internal nodes are repeatedly precharged and discharged at every clock cycle even when they are evaluating the same value. Hence, they consume a large amount of power regardless of input statistics. This flip-flop design technique eliminates unnecessary transitions to minimize power with no impact on speed.