A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications

Abstract

A transmit architecture with a programmable 4-tap feedforward equalizer for 6.25 to 12.5 Gb/s serial communications through lossy channels is described. A 16:8-channel MUX/DEMUX chip fabricated in a 0.13 /spl mu/m 7M CMOS process demonstrates a near-end jitter of 16 ps and an equalized far-end jitter of 55 ps at 6.25 Gb/s over a 36'' legacy backplane channel.